NXP Semiconductors /MIMXRT1011 /SNVS /HPSR

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Interpret as HPSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HPTA_0)HPTA 0 (PI_0)PI 0 (LPDIS)LPDIS 0 (BTN)BTN 0 (BI)BI 0 (SSM_STATE_0)SSM_STATE 0 (FAB_CONFIG)SECURITY_CONFIG 0OTPMK_SYNDROME0 (OTPMK_ZERO_0)OTPMK_ZERO 0 (ZMK_ZERO_0)ZMK_ZERO

ZMK_ZERO=ZMK_ZERO_0, SECURITY_CONFIG=FAB_CONFIG, SSM_STATE=SSM_STATE_0, OTPMK_ZERO=OTPMK_ZERO_0, HPTA=HPTA_0, PI=PI_0

Description

SNVS_HP Status Register

Fields

HPTA

HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared.

0 (HPTA_0): No time alarm interrupt occurred.

1 (HPTA_1): A time alarm interrupt occurred.

PI

Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared.

0 (PI_0): No periodic interrupt occurred.

1 (PI_1): A periodic interrupt occurred.

LPDIS

Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS

BTN

Button Value of the BTN input

BI

Button Interrupt Signal ipi_snvs_btn_int_b was asserted.

SSM_STATE

System Security Monitor State This field contains the encoded state of the SSM’s state machine

0 (SSM_STATE_0): Init

1 (SSM_STATE_1): Hard Fail

3 (SSM_STATE_3): Soft Fail

8 (SSM_STATE_8): Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)

9 (SSM_STATE_9): Check

11 (SSM_STATE_11): Non-Secure

13 (SSM_STATE_13): Trusted

15 (SSM_STATE_15): Secure

SECURITY_CONFIG

Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS

0 (FAB_CONFIG): FAB configuration

1 (OPEN_CONFIG): OPEN configuration

2 (OPEN_CONFIG): OPEN configuration

3 (OPEN_CONFIG): OPEN configuration

4 (FIELD_RETURN_CONFIG): FIELD RETURN configuration

8 (FAB_CONFIG): FAB configuration

9 (CLOSED_CONFIG): CLOSED configuration

10 (CLOSED_CONFIG): CLOSED configuration

11 (CLOSED_CONFIG): CLOSED configuration

OTPMK_SYNDROME

One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location

OTPMK_ZERO

One Time Programmable Master Key is Equal to Zero

0 (OTPMK_ZERO_0): The OTPMK is not zero.

1 (OTPMK_ZERO_1): The OTPMK is zero.

ZMK_ZERO

Zeroizable Master Key is Equal to Zero

0 (ZMK_ZERO_0): The ZMK is not zero.

1 (ZMK_ZERO_1): The ZMK is zero.

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